In many software-defined radio (SDR) applications, such as Tactical Data Radio Systems (TDRS), there are significant portions of the waveform that reside in VHSIC (very-high-speed integrated circuit) hardware description language (VHDL). In many SDR applications, the portions of the waveform that reside in VHDL are implemented utilizing FPGA's (field-programmable gate array). As designs for SDR applications become more FPGA intensive, the capacity of designs may be limited by hardware resources, clock speeds, thermal requirements, etc. When the capacity of the design is limited, it is often critical to get the sample rate down quickly without requiring a lot of excess logic. Although the first stage of decimation (a technique for reducing the number of samples in a discrete-time signal) is traditionally provided by feeding an oversampled sequence into a CIC (cascaded integrator comb) filter, even this may require more logic than can be spared for a given application.
Referring generally to FIG. 1; the traditional breakdown of signal processing within a SDR application, as is known in the art, is illustrated. The intermediate frequency (IF) signal is fed into an analog-to-digital converter 101. The converted signal is separately mixed 104 and 105 with an in-phase component 102 and a quadrature component 103. The in-phase signal and quadrature signal are then separately filtered 106 and 107 and the sample rate of each is separately reduced 108 and 109. When the sample rate is related to the IF signal frequency such that fif is a factor of ¼ or ¾ for fs, the mixer sequences simplify to a {1, 0, −1, 0} sequence for the in-phase signal and a {0, −1, 0, 1} or {0, 1, 0, −1} for the quadrature signal. A representation of the quadrature mix is shown in FIG. 2.
Consequently, it would be desirable to provide a quick, low-distortion and efficient reduction in sample rate requiring minimal logic.